View MEA224_4639105.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

obsolescence notice this product is obsolete. this information is available for your convenience only. for more information on zarlink?s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/
? 1997 zarlink semiconductor inc. page: 1 r ev. 4.0 Cdecember, 1997 p reliminary data sheet ea-224 C 4-port fast ethernet access controller (xpressflow tm 2001 series 10/100 ethernet switch chipset) 1. distinctive characteristics 4 independent 10/100mbps ethernet access ports 9 di rect interface with 10baset transceiver 9 ieee 802.3u compliant mii ( media independent in- terface ) and serial management interface 9 di rect interface with 100basetx, -t2, -t4, or -tf physical transceivers state of the art 0.5 micron 3.3volt cmos process 352-pin bga package o perating frequency 9 -33 33 mhz maximum 9 -40 40 mhz maximum 9 -50 50 mhz maximum 32-bit local buffer memory interface 9 supports 128k to 1m bytes 9 ut ilize high performance 32-bit synchronous burst sram ha rdware assisted buffer and queue management to minimized cpu overhead 16-bit processor bus i/o interface 9 allows host to access control registers & local buffer memory 9 supports big and little endian cpus 9 di rect interface with various different standard microprocessors including 386, 486 families and mo torola mpc series embedded processors. 32-bit xpressflow bus interface 9 us es granule for frame transferring between access controllers supports unicast, multicast, and broadcast frames 9 also detects ieee 802.3x mac control frames wo rks together with sc-201 xpressflow engine 9 capable to forward frames at full line-rate 9 di stributed flow caching? to reduce frame for- wa rding latency supports both half & full duplex operation programmable flow control enable 9 jam fake collision for half duplex mode 9 tr ansmit flow control frame for ieee 802.3x full duplex mode th ree frame forwarding modes 9 store-&-forward 9 safe cut-thru (runt free) 9 tu rbo cut-thru (10mbps mode only) 9 automatically selects the optimized mode for forwarding 9 allows manual frame forwarding mode selection override mu lti-media ready with qos supports 9 four frame transmission priority queues complies with ieee 802.1 bridge standard 9 assigns one unique mac address for each port vlan id tagging & stripping 9 auto padding if necessary after stripping automatic retry frame transmission 9 tr ansmit collision 9 tr ansmit buffer under-run automatic receive filtering for bad frames for store & forward mode 9 bad fcs 9 short events or frames under 64 bytes 9 long events or frames over 1518 bytes automatic statistic collection for rmon local bu ffer memory m anagement bus xpre ssflow bus 16 32 32 ea- 224 4-port ethernet ac ce ss controller 10/100m basetx xceiver port 1 port 3 port 2 port 0 10/100m basetx ports
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 2 rev. 4.0 Cdecember, 1997 2. general description: t he ea-224 provides four 10/100mbps ethernet network ac- ce ss interface ports. mii interface is used to connect external phy devices for 100 mbps ethernet. t hey also can direct connect with st andard 10mbps serial interface. t he ea-224 provides the ethernet mac protocols, handles the local buffer memory interface and m anagement, arbitrates among m ultiple priority queues, and in- terfaces with the xpr e ssflow en- gine and other access controllers through the xpr e ssflow mess age passing protocol. 2.1 related components: sc-201 C xpressflow engine ea-208e C 8-port 10mbps ethernet access controller ea-208 C 6-port 10 + 2-port 10/100 ethernet access con- troller ea-222 C 2-port 10/100 fast ethernet access controller 2.2 typical application: a 16-port ethernet switch with 4 fast ethernet up-links local bu ffer memory m anagement bus swit ch bus switch bus interafce mac port #0 to #3 port 0 2 3 16 32 32 4-port 100base-tx phy m anagem bu s interafce local bu ffer memory interface automa tic bu ffer m anager ma c interface 1 port 0 2 3 1 32 32 ea-224 block diagram C ea-224 4-port ethernet access controller address m apping t able flash rom sc 201 x pressflow e ngine ea20 8e 8-port et hernet access controller management bus bu ffer ram switch ma nager cpu dram rs232 local control cons ole bu ffer ram 8 ethernet ports bu ffer ram 8 ethernet ports xpressflow bus ea20 8e 8-port eth ernet access controller bu ffer ram four 100m fast ethernet ports ea224 4-port eth ernet access controller system block diagram -- 16-port ethernet switch with 4 fast ethernet up-links
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 3 rev. 4.0 Cdecember, 1997 3. pin assignment 3.1 logic symbol ea-224 t_mode m_mdc m_mdio xpressflow bus interface management bus interface test pin p_d[15:0] p_cs# p_ads# p_rwc p_bs16# p_rdy# p_int p_rst# p_clk p_a[11:1] control buffer memory interface mii serial mana g em't mm_rxd[3:0] mm_rxdv mm_rxc mm_rxer 4 mm_txer mm_txc mm_txen mm_txd[0] mm_txd[1] mm_txd[2] mm_txd[3] port [3:0] 10/100 mii interface mm_col mm_crs mm_lnk tm_rxd tm_rxc tm_txc tm_txen tm_txd tm_lpbk tm_fd tm_col tm_crs tm_lnk mii mode 10baset serial xface s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_ovld# s_hpreq# s_req# s_gnt# s_clk l_d[31:0] l_oe[3:0]# l_adsc# l_clk l_a[18:2] l_we[3:0]# l_bwe[3:0]# 4 4 4
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 4 rev. 4.0 Cdece mber, 1997 3.2 pin assignment (preliminary) note: #a ct ive low signal input input signal i-st input signal with schmitt-trigger ou tput output signal (tri-state driver) ou t-od output signal with open-drain driver i/o-ts input & output signal with tri-state driver i/o-od input & output signal with open-drain driver 5vt input with 5v tolerance ou tput signal with programmable polarity. input or output pins with weak internal pull up resistors (50k to 100k ohms each) t hese pins are reserved for internal use only. they should be left unconnected. pin no(s). symbol type max i ol / i oh name & functions ma nagement bus interface j25,k26,l24,k25,l26, m 24,l25,m26,n24,m25, p24,n26,n25,r24,p26, p25 p_d[15:0] ttl i/o-ts (5vt) 16ma management bus C data bit [15:0] c26,d24,c25,e24,d26, d25,f24,e26,e25,g24, f26 p_a[11:1] ttl in (5vt) management bus C address bit [11:1] f25 p_ads# ttl in (5vt) management bus C address strobe h25 p_rwc ttl in (5vt) management bus C read/write control j24 p_rdy# ttl out-od 16ma management bus C data ready g2 5p _bs16# ttl out-od 16ma management bus C 16 bit data bus g2 6p _cs# ttl in (5vt) management bus C chip select h26 p_int cm os output 4ma management bus C interrupt request j26 p_rst# ttl in-st (5vt) m anagement bus C master reset k24 p_clk ttl in (5vt) management bus C bus clock xpressflow bus interface c23,a23,b22,c22,a22 s_d[31:27] / p_c[0:4] cmos i/o-ts 12 ma xpressflow bus C data bit [31:27] or m anagement bus interface configuration bit [0:4] b21,d20,c21,a21,b20, a20,c20,b19,a19,c19, b18,a18,b17,c18,a17, d17,b16,c17,a16,b15, a15,c16,b14,d15,a14, c15,b13 s_d[26:0] cmos i/o-ts 12ma xpressflow bus C data bit [26:0] b12 s_msgen# cmos i/o-ts 12 ma xpressflow bus C message envelope a12 s_eof# cmos i/o-ts 12ma xpressflow bus C end of frame c14 s_irdy cmos i/o-ts 12 ma xpressflow bus C initiator ready c13 s_tabt# cmos i/o-od 12 ma xpressflow bus C target abort b23 s_hpreq# cmos i/o-od 12ma xpressflow bus C high priority request a24 s_req# cmos output 4ma xpressflow bus C bus request to sc201 b24 s_gnt# cmos input xpressflow bus C bus grant from sc201 a13 s_ovld# cmos input xpressflow bus C bus overload d1 3s _clk cmos input xpressflow bus C clock
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 5 rev. 4.0 Cdece mber, 1997 pin no(s). symbol type max i ol / i oh name & functions control buffer memory interface m4 ,n2,l3,m1,m2,l1,k3, l2,k4,k1,j3,k2,j1,j2, h3,h1,h2,g3,g1,g2,f1, f3,f2,e1,e3,e2,d1,d3, d2,c1,c2,b1 l_d[31:0] ttl i/o-ts 8ma local memory bus C data bit [31:0] a6,b6,c8,a7,d8,d7,c9, a8,b8,a9,c10,b9,d10, a10,c11,b10,a11 l_a[18:2] cmos output 8ma local memory bus C address bit [17:2] c7 l_a[19] / l_oe[3]# cm os ou tput 8ma local memory bus C address bit [19] or me mory read chip select [3] d5 ,a5,a3 l_oe[2:0]# cmos output 2ma local memory read chip select [2:0] d7,e4,b5,c4 l_we[3:0]# cmos output 2ma local memory write chip select [3:0] c6 ,b4,a4,c5 l_bwe[3:0]# cmos output 8ma local memory byte write enable, byte [3:0] b3 l_adsc# cmos output 8ma local memory controller address status g4 l_clk cmos output 8ma local memory clock input fast ethernet access port [3:0] t2 4m _mdc cmos output 4ma mii management data clock C (common for all mii ports C port [1:0]) r26 m_mdio ttl io-ts (5vt) 4ma mii management data i/o C (common for all mii ports C port [1:0])) ab2,u25,ae26,af5 m[3:0]_rxd[3] ttl in (5vt) port [3:0] C mii receive data bit [3] ab1,v24,ad25,ae6 m[3:0]_rxd[2] ttl in (5vt) port [3:0] -- receive data bit [2] aa3,u26,ad26,ad6 m[3:0]_rxd[1] ttl in (5vt) port [3:0] -- receive data bit [1] ac2,t25 m[3:2]_rxd[0] ttl in (5vt) port [3:0] -- receive data bit [0] ac25,af6 m[1:0]_rxd[0] ttl in (5vt) y3 ,v26,af24,ad5 m[3:0]_rxdv ttl in (5vt) port [3:0] -- receive data valid ac1,u24 m[3:2]_rxc ttl in (5vt) port [3:0] -- receive clock ac24,ae7 m[1:0]_rxc ttl in (5vt) aa1,v25,ad23,ae5 m[3:0]_rxer port [3:0] -- receive error aa2,w24,ae24,af4 m[3:0]_txer cmos output 4ma port [3:0] -- transmit error w2 ,aa25,ae22,ad1 m[3:0]_txc ttl in (5vt) port [3:0] -- transmit clock w1 ,aa24,af22,af2 m[3:0]_txen cmos output 4ma port [3:0] -- transmit enable v3,aa26,ad21,ae3 m[3:0]_txd[3] cmos output 4ma port [3:0] -- transmit data bit [3] y2 ,y26,ae23,af3 m[3:0]_txd[2] cmos output 4ma port [3:0] -- transmit data bit [2] w3 ,w26,ad22,ad4 m[3:0]_txd[1] cmos output 4ma port [3:0] -- transmit data bit [1] y1 ,w25,af23,ae4 m[3:0]_txd[0] cmos output 4ma port [3:0] -- transmit data bit [0] v1,ab26 m[3:2]_col ttl in (5vt) port [3:0] -- collision detected ad20,ac3 m[1:0]_col ttl in (5vt) u3,ab24 m[3:2]_crs ttl in (5vt) port [3:0] -- carrier sense af21,ad2 m[1:0]_crs ttl in (5vt) v2,ab25 m[ 3:2]_lnk ttl in (5vt) port [3:0] -- link status ae21,ab3 m[ 1:0]_lnk ttl in (5vt) test facility a25 t_mode cmos i/o-ts 2ma test pin C set test mode upon reset, and provides test status output during test mode n1,m3,p2,p1,n3,r2,p3, r1,t2,r3,t1,r4,u2,t3, u1,u4 t_ d[ 15:10] cm os ou tput 4ma test pins C reserved for internal use only
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 6 rev. 4.0 Cdece mber, 1997 pin no(s). symbol type name & functions power pins d6 ,d11,d16,d21,f4, f23,l4,l23,t4,t23,aa4, aa23,ac6,ac11,ac16, ac21 vdd power +3.3 volt dc supply a1,a2,a26,b2,b25,b26, c3 ,c24,d4,d9,d14,d19, d23,h4,j23,n4,p23,v4, w 23,ac4,ac8,ac13, ac18,ac23,ad3,ad24, ae1,ae2,ae25,af1, af25 vss power ground
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 7 rev. 4.0 Cdece mber, 1997 3.3 pin reference table: (352 pin bga) pin # si gnal name pin # signal name pin # signal name pin # signal name pin # si gnal name f26 p_a[1] d 17 s_d[11] d2 l_d[3] af23 m1_txd[0] / t1_txd r1 t_d[8] g24 p_a[2] a17 s_d[12] d3 l_d[4] af22 m1_txen / t1_txen p3 t_d[9] e25 p_a[3] c18 s_d[13] d1 l_d[5] ae22 m1_txc / t1_txc r2 t_d[10] e26 p_a[4] b17 s_d[14] e2 l_d[6] ae24 m1_txer n3 t_d[11] f24 p_a[5] a 18 s_d[15] e3 l_d[7] ad23 m1_rxer p1 t_d[12] d25 p_a[6] b 18 s_d[16] e1 l_d[8] ac24 m1_rxc / t1_rxc p2 t_d[13] d26 p_a[7] c 19 s_d[17] f2 l_d[9] af24 m 1_rxdv m3 t_d[14] e24 p_a[8] a19 s_d[18] f3 l_d[10] ac25 m1_rxd[0] / t1_rxd n1 t_d[15] c25 p_a[9] b 19 s_d[19] f1 l_d[11] ad26 m1_rxd[1] d24 p_a[10] c2 0s_d[ 20] g2 l_d[12] ad25 m1_rxd[2] d6 vdd c26 p_a[ 11] a20 s_d[21] g1 l_d[13] ae26 m1_rxd[3] d11 vdd f25 p_ads# b 20 s_d[22] g3 l_d[14] ab25 m2 _lnk / t2_lnk d16 vdd g26 p_cs# a21 s_d[23] h2 l_d[15] ab24 m2_ crs / t2_crs d21 vdd h25 p_rwc c2 1s_d[ 24] h1 l_d[16] ab26 m2_col / t 2_col f4 vdd g25 p_bs16# d20 s_d[25] h3 l_d[17] aa26 m2_txd[3] / t2_fd f23 vdd j24 p_ rdy# b21 s_d[26] j2 l_d[18] y26 m2_txd[2] / t2_lpbk l4 vdd j26 p_rst# a 22 s_d[27] / p_c[4] j1 l_d[19] w26 m 2_txd[1] l23 vdd h26 p_int c22 s_d[ 28] / p_c[3] k2 l_d[20] w25 m2_txd[0] / t2_txd t4 vdd k24 p_clk b22 s_d[29] / p_c[2] j3 l_d[21] aa24 m2_txen / t2_txen t23 vdd p25 p_d[0] a23 s_d[30] / p_c[1] k1 l_d[22] aa25 m2_txc / t2_txc aa4 vdd p26 p_d[1] c23 s_d[31] / p_c[0] k4 l_d[23] w24 m 2_txer aa23 vdd r24 p_d[2] l2 l_d[24] v25 m2_rxer ac6 vdd n25 p_d[3] a 11 l_a[2] k3 l_d[25] u24 m 2_rxc / t2_rxc ac11 vdd n26 p_d[4] b 10 l_a[3] l1 l_d[26] v26 m2_rxdv ac16 vdd p24 p_d[5] c11 l_a[4] m2 l_d[27] t25 m2_rxd[0] / t2_rxd ac21 vdd m25 p_d[6] a 10 l_a[5] m1 l_d[28] u26 m2_rxd[1] a1 gnd n24 p_d[7] d 10 l_a[6] l3 l_d[29] v24 m2_rxd[2] a2 gnd m26 p_d[8] b9 l_a[7] n2 l_d[30] u25 m2_rxd[3] a26 gnd l25 p_d[9] c10 l_a[8] m4 l_d[31] v2 m3 _lnk / t3_lnk b2 gnd m24 p_d[ 10] a9 l_a[9] u3 m3_ crs / t3_crs b25 gnd l26 p_d[11] b8 l_a[10] t24 m_mdc v1 m3_col / t3_col b26 gnd k25 p_d[12] a8 l_a[11] r26 m_mdio v3 m3_txd[3] / t3_fd c3 gnd l24 p_d[13] c9 l_a[12] y2 m3_txd[2] / t3_lpbk c24 gnd k26 p_d[14] b7 l_a[13] ab3 m 0_lnk / t0_lnk w3 m 3_txd[1] d4 gnd j25 p_d[ 15] d8 l_a[14] ad2 m0_crs / t0_crs y1 m3_txd[0] / t3_txd d9 gnd a7 l_a[15] ac3 m0_col / t0_col w1 m 3_txen / t3_txen d14 gnd d13 s_clk c8 l_a[16] ae3 m0_txd[3] / t0_fd w2 m 3_txc / t3_txc d19 gnd a13 s_ovld# b6 l_a[17] af3 m0_txd[2] / t0_lpbk aa2 m3_txer d23 gnd b23 s_hpreq# a6 l_a[18] ad4 m0_txd[1] aa1 m3_rxer h4 gnd a24 s_req# c7 l_a[19] / oe[3]# ae4 m0_txd[0] / t0_txd ac1 m 3_rxc / t3_rxc j23 gnd b24 s_gnt# d5 l_oe[2]# af2 m0_txen / t0_txen y3 m3_rxdv n4 gnd b12 s_msgen# a5 l_oe[1]# ad1 m0_txc / t0_txc ac2 m3_rxd[0] / t3_rxd p23 gnd a12 s_eof# a3 l_oe[0] af4 m0_txer aa3 m3_rxd[1] v4 gnd c14 s_irdy d7 l_we[3]# ae5 m 0_rxer ab1 m3_rxd[2] w23 gnd c13 s_t abt# e4 l_we[2]# ae7 m0_rxc / t0_rxc ab2 m3_rxd[3] ac4 gnd b13 s_d[0] b5 l_we[1]# ad5 m 0_rxdv ac8 gnd c15 s_d[1] c4 l_we[0]# af6 m0_rxd[0] / t0_rxd a25 t_mode ac13 gnd a14 s_d[2] c6 l_bwe[3 ]# ad 6 m0_rxd[1] ac18 gnd d15 s_d[3] b4 l_bwe[2 ]# ae6 m0_rxd[2] u4 t_d[0] ac23 gnd b14 s_d[4] a4 l_bwe[1 ]# af 5 m0_rxd[3] u1 t_d[1] ad3 gnd c16 s_d[5] c5 l_bwe[0 ]# ae21 m 1_lnk / t1_lnk t3 t_d[2] ad24 gnd a15 s_d[6] b3 l_adsc# af 21 m1_crs / t1_ crs u2 t_d[3] ae1 gnd b15 s_d[7] g4 l_clk ad20 m1_col / t1_col r4 t_d[4] ae2 gnd a16 s_d[8] b1 l_d[0] ad21 m1_txd[3] / t1_fd t1 t_d[5] ae25 gnd c17 s_d[9] c2 l_d[1] ae23 m1_txd[2] / t1_lpbk r3 t_d[6] af1 gnd b16 s_d[10] c1 l_d[2] ad22 m1_txd[1] t2 t_d[7] af25 gnd note: ou tput signals with programmable polarity. input or output pins with weak internal pull up resistors (50k to 100k ohms each) t hese pins are reserved for internal use only. they should be left unconnected.
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 8 rev. 4.0 Cdece mber, 1997 4. functional description 4.1 local memory (local buffer memory) interface use industry standard synchronous burst mode sram up to 1m bytes 9 32k x 32, 64k x 32, 128k x 32, or 256k x 32 provides 4 individual byte write enable controls ( l_bwe[3:0]# ) provides separate read and write chip selects ( l_oe[3:0]# and l_we[3:0]# ) for each memory chip supports back to back read or write operations across memory chips 4.1.1 pin description sy mbol type name & functions l_d[31:0] ttl i/o-ts local memory data bus bit [31:0] C a 32-bit synchronous data bus. l_a[18:2] cmos out put local memory address bus bit [18:2] C bit [18:2] of a synchronous address bus. the memory address is sampled when l_cs# is enabled and l_adsc# is asserted. l_a[19] / l_oe[3]# cmos out put local memory address bus bit [19] or local memory read chip select [3] C depends on memory configuration, this pin can be used as the local memory address bit [19] or as the local memory read chip select [3]. l_oe[2:0]# cmos out put local memory read chip select [2:0] C allows up to read one of the 4 banks of memory. l_we[3:0]# cmos out put local memory write chip select [3:0] C allows up to write one of the 4 banks of memory. l_bwe[3:0]# cmos out put local memory byte write enable [3:0] C use to write individual bytes. l_adsc# cmos out put local memory controller address status C to load a new address. l_clk cmos out put local memory clock C a synchronous clock to memory devices. note: t hese pins have weak internal pull up resistors (50k to 100k ohms each).
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 9 rev. 4.0 Cdece mber, 1997 4.1.2 supported memory configurations read/write chip select and high address bits chip #3 chip #2 chip #1 chip #0 ram chip size # of ram chips total buffer memory size l_ we[3]# l_ a[19] / l_ oe [3]# l_ we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 32k x 32 1 128k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 256k bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 512k bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 64k x 32 1 256k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 512k bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 1m bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 128k x32 1 512k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 1m bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 256k x32 1 1m bytes ---- l_a[19] ---- ---- ---- ---- l_we[0]# l_oe[0]# 4.1.3 bus cycle waveforms a1 a2 a3 a3+1 a3+2 a3+3 a4 a4+1 a4+2 a4+3 a5 a6 d2 d3+1 d3+2 d3+3 d4 d4+1 d4+2 d4+3 d5 d6 d1 d3 l_clk l_ads c# l_cs# l_a[19:2] l_we[3:0]# l_bwe[3:0]# l_oe[3:0]# l_d[31:0] (wr) l_d[31:0] (rd) typical local memory access operations
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 10 rev. 4.0 Cdecember, 1997 4.2 management bus interface supports various industry standard micro- processors including: 9 intel 186, 386, and 486 family or equivalent 9 motorola mpc series embedded processors easily adapts to other industry standard cpus provides separate address and data bus supports big & little endian byte ordering supports 16-bit data bus supports early rdy cycle 9 meets timing requirement for intel/amd 186 family processors supports 1x or 2x cpu clock 9 2x cpu clock for 386 family processors provides a single interrupt signal to switch manager cpu 4.2.1 pin description sy mbol type name & functions p_c[4:0] cmos input processor configuration bit [4:0] : C during the reset cycle, the p_c[4:0] pins provides the processor configuration. by using external w eak pull-up or -down resistors, they define the external management bus interface configuration. these inputs are sampled at the trailing edge of the reset cycle. c[ 0] C defines the cpu clock input is 1x or 2x clock c[1] C selects either big or little endian byte ordering c[2] C defines the polarity of the p_rwc (rd/wr control) input c[ 3] C defines the cpu bus width C for ea-208, it is default to 16-bit cpu bus interface, and the setting of this bit is ignored. c[ 4] C defines the timing relationship between p_rdy and p_d[15:0] valid. if c[4] is high, the p_d[15:0] are valid along in the same clock period as p_rdy is asserted. if c[4] is low, the p_rdy is asserted one clock period early ahead of the p_d[15:0] are valid. c[0] c[1] c[2] c[3] c[4] cpu clock byte order rwc bus size rdy timing lo 1x clock little endian p_r/w# n/a normal hi 2x clock big endian p_w/r# n/a early after reset, these pins are used as xpr e ssflow bus data bit [31:27]. p_a[11:1] ttl in (5vt) address bus bit [11:1] C i/o port address p_d[15:0] ttl i/o-ts (5vt) data bus bit [15:0] C a 16-bit synchronous data bus. p_ads# ttl in (5vt) address strobe C indicates valid address is on the bus p_rwc ttl input (5vt) read/write control C indicates the current bus cycle is a read or write cy cl e. c[1] defines the polarity of this signal during the reset cycle. c[1]=0 p_r/w# is used for powerpc or other similar processors. c[1]=1 p_w/r# is used for 386, 486 or other similar processors p_ rdy# ttl out-od data ready C timing indicates for bus data valid p_bs16# ttl out-od bus size 16 C response to bus master that the ea208 only supports 16- bit data bus width. p_cs# ttl input (5vt) chip select C indicates the xpr e ssflow engine is the target for the cur- r ent bus operation. p_int cmos out- put interrupt request to switch manager cpu the polarity of this signal output is programmable via chip configuration register . p_rst# ttl in-st (5vt) cpu reset C synchronous reset input from switch manager cpu p_clk ttl in (5vt) cpu clock C 2x clock for 386 family, and 1x clock for the others
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 11 rev. 4.0 Cdecem ber, 1997 4.2.2 motorola mpc801 processor interface p_clk {clkout} p_ads# {ts#} p_a[11:1] {a[20:30]} p_cs# p_rwc {rd/wr#} p_rdy# {ta#} p_d[15:0] {d[0:15]} p_d[15:0] {d[0:15]} (out) (in) note: mnemonics with in {} are the equivalent signals defined by mpc801 typical motorola mpc801 cpu i/o access operations 4.2.3 intel 486 processor interface p_clk p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[15:0] (in) p_d[15:0] (out) typical 486 cpu i/o access operations
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 12 rev. 4.0 Cdecember, 1997 4.2.4 intel 386 processor interface ph2 p_clk ph2 (internal) p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[15:0] (in) p_d15:0] (out) typical 386 cpu i/o access operations ph2 ph1 ph2 or ph1 ph2 p_clk ph2 (internal) p_rst# internal ph2 clock synchronization ** note: ** see intel 386 processor data book for more details
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 13 rev. 4.0 Cdecem ber, 1997 4.2.5 register map note: all 32-bit registers are d-word aligned. all 16-bit registers are also d-word aligned and right justified. for the little endian cpus, register offset bit [1,0] are always set to be 00. for the big endian cpus, register offset bit [1,0] are always set to be 10. t his is a global register. cpu is allowed to write the global register of all devices by a sin- gle operation. t hese registers are reserved for system diagnostic usage only. i/o offset register description little e ndian big e ndian reg. size w/r note: device configuration registers (dcr) gc rg lobal control register hf00 hf02 16-bit w/-- dcr0 device status register hf00 hf02 16-bit --/r dcr1 signature & revision register hf10 hf12 16-bit --/r dcr2 id register hf20 hf22 16-bit w/r dcr3 device configuration register hf30 hf32 16-bit w/r dcr4 interfaces status register hf40 hf42 16-bit --/r dtsr test register hf70 hf72 16-bit w/r interrupt controls isr interrupt status register C unmasked hf80 hf82 16-bit --/r isrm interrupt status register C masked hf90 hf92 16-bit --/r imsk interrupt mask register hfa0 hfa2 16-bit w/r iar interrupt acknowledgment register hfb0 hfb2 16-bit w/-- buffer memory interface mwar memory write address reg. C single cycle he08 he08 32-bit w/r mrar memory read address reg. C single cycle he18 he18 32-bit w/r mbar memory address register C burst mode he28 he28 32-bit w/r mwbs memory write burst size (in d-words) he40 he42 16-bit w/r mrbs memory read burst size (in d-words) he50 he52 16-bit w/r mwdr memory write data register he68 he68 32-bit w/-- mwdx memory write data reg. C byte swapping he6c he6c 32-bit w/-- mrdr memory read data register he68 he68 32-bit --/r mrdx memory read data reg. C byte swapping he6c he6c 32-bit --/r fcb buffer & stack management fcbba frame control buffer C base address hd00 hd02 16-bit w/r fcbag frame control buffer C buffer aging status hd30 hd32 16-bit --/r fcbsl frame ctrl buffer stack C size limit hd90 hd92 16-bit w/r fcbst frame ctrl buffer stack C buffer low threshold hda0 hda2 16-bit w/r fcbss frame ctrl buffer stack C allocation status hdb0 hdb2 16-bit --/r
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 14 rev. 4.0 Cdecem ber, 1997 i/o offset register description little e ndian big e ndian reg. size w/r note: access control function (chip level controls) avxr vlan control table (vct) index register hc00 hc02 16-bit w/-- avdr vct data register hc10 hc12 16-bit w/r avtc vlan type code hc20 hc22 16-bit w/r axsc transmission scheduling control register hc30 hc32 16-bit w/r amiic mii command register hc40 hc40 32-bit w/-- amiis mii status register hc40 hc40 32-bit --/r afcr flow control register hc70 hc72 16-bit w/r amar0 multicast address. for mac control frames byte [1,0] hc80 hc82 16-bit w/r amar1 byte [3,2] hc90 hc92 16-bit w/r amar2 byte [5,4] hca0 hca2 16-bit w/r amct mac control frametype code register hcb0 hcb2 16-bit w/r adar0 base mac address register C byte [1,0] hcc0 hcc2 16-bit w/r adar1 base mac address register C byte [3,2] hcd0 hcd2 16-bit w/r adar2 base mac address register C byte [5,4] hce0 hce2 16-bit w/r ethernet mac port control registers C (substitute [n] with port number, n = {0..3] ) ecr0 mac port control register h n 00 h n 02 16-bit w/r ecr1 mac port configuration register h n 10 h n 12 16-bit w/r ecr2 mac port interrupt mask register hn20 hn22 16-bit w/r ecr3 mac port interrupt status register hn30 hn32 16-bit --/r exsr mac tx status register hn40 hn42 16-bit --/r exec mac tx error counters hn50 hn52 16-bit --/r ersr mac rx status register hn68 hn68 32-bit --/r erec mac rx error counters hn78 hn78 32-bit --/r
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 15 rev. 4.0 Cdecem ber, 1997 4.3 xpressflow bus operation zarlinks optimized xpr e ssflow bus architec- ture provides up to 1.6g bps switching bandwidth 9 -33 1. 07g bps 9 -40 1. 28g bps 9 -50 1. 60g bps fu ll multi bus master structure allows access controllers to communicate with xpr e ssflow engine and other access controllers via a message passing protocol tw o level bus request priorities 9 high priority for data messages z for forwarding an ethernet frame from re c eiving port to transmission port 9 low priority for command messages z for passing control information between devices 4.3.1 pin description sy mbol type name & functions s_d[31:0] cmos i/o-ts data bus bit [31:0] C a 32-bit synchronous data bus. note: during the system reset period, data bit [31:27] are used as processor interface configuration bit [0:3] s_msgen# cmos i/o-ts m essage envelope C encompasses the entire period of a message transfer. targets use the leading edge of this signal to detect the be- ginning of a message transfer, and to decode the message header for the intended target(s). s_eof# cmos i/o-ts e nd of frame C only used by frame data transfer messages to identify the end of frame condition. this signal is synchronous with the rx frame status word appended to the end of the message. s_irdy cmos i/o-ts initiator ready C a normal true signal. when negated, it indicates the initiator had asserted wait state(s) in between command words. target s hould use this signal as enable signal for latching the data from the bus. s_tabt# cmos i/o-od target abort C when asserted, the target had aborted the reception of cu rr ent message on the bus. s_hpreq# cmos i/o-od high priority request C indicates one or more bus requester is re- questing for high priority message transfer. s_req# cmos out put bus request C bus request signal from access controller to bus ac- cess arbit rator in xpr e ssflow engine s_gnt# cmos input bus grant C bus grant signal from bus arbitrator to bus requester s_ovld# cmos input bus over-load C when asserted, all data forwarding bus bandwidth has been allocated. cannot support additional load for data forwarding traf- fic. s_clk cmos input xpressflow bus clock C up to 50mhz system clock
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 16 rev. 4.0 Cdecem ber, 1997 4.3.2 bus cycle waveforms c0 d5 eof d2 c1 d0 d1 d3 d4 s_clk s_msgen# s_d[31:0] s_eof# s_irdy xpressflow bus data transfer cycle command cycle data xfer w/o data c0 c1 c0 c1 eof c1 c0 aborted command s_clk s_msgen# s_d[31:0] s_eof# s_tabt# other xpressflow bus cycles s_clk s_req[k]# s_req[j]# s_hpreq# high priority request pre-empts the low priority request.
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 17 rev. 4.0 Cdecem ber, 1997 s_clk s_msgen# s_req[j]# s_gnt[j]# s_hp req# s_req[i]# s_gnt[i]# xpressflow bus arbitration s_clk s_req[k]# s_ovld# bus overload pre-empts the data transfer request
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 18 rev. 4.0 Cdecem ber, 1997 4.4 mii interface fully compliant with ieee 802.3u media inde- pendent interface for connecting with external 10/100m ethernet physical layer transceiver supports both 10mbps 10baset interface and 100mbps 100basetx interface supports both half and full duplex operation shared station management interface (one for all mii channels with in the access controller) all ports can also support 10mbps serial in- terface 9 if 10mbps serial interface is used, the mii port pin assignment are re-mapped for 10mbps serial interface. 4.4.1 pin description sy mbol type name & functions m_mdc cmos out put m ii management data clock C (common for all mii ports) used to syn- ch r onize the mii data stream (mdio) for transferring between the ac- ce ss controller and the mii tranceivers. m_mdio ttl io-ts (5vt) m ii management data i/o C (common for all mii ports) a serial man- agement data stream synchronous with mdc. mm _ rxd[3:0] ttl in (5vt) receive data [3:0] C (one set for each mii port) a four-bit transmit data nibble. bit 0 is the least significant bit, and bit 3 is the most significant bit. mm_rxdv ttl in (5vt) receive data valid C (one for each mii port) instructs the mac to be- gin moving data nibbles from the receive data lines. mm_rxc ttl in (5vt) receive clock C (one for each mii port) a 25mhz clock input with 35% to 65% duty cycles. mm_rxer ttl in (5vt) receive error C (one for each mii port) mm_txer cmos out put transmit error C (one for each mii port) mm_txc ttl in (5vt) transmit clock C (one for each mii port) a continuous clock input with 35% to 65% duty cycles. mm_txen cmos out put transmit enable C (one for each mii port) instructs the transceiver to begin moving data nibbles on the transmit data lines. mm_txd[3:0] cmos out put transmit data [3:0] C (one set for each mii port) a four-bit transmit data nibble. bit 0 is the least significant bit, and bit 3 is the most signifi- c ant bit. mm_col ttl in (5vt) collision detected C (one for each mii port) mm_crs ttl in (5vt) carrier sense C (one for each mii port) mm_lnk ttl in (5vt) link status C (one for each mii port) th e polarity of this signal is programmable via port configuration reg- ister note: m is the port number [3:0]. th ese signals have programmable output polarity.
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 19 rev. 4.0 Cdecem ber, 1997 40 nsec txc txen tx d[3:0] 100m mii transmit timing 40 nsec 40 nsec data sfd sfd rxc rxdv rxd[3:0] 100m mii receive timing
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 20 rev. 4.0 Cdecem ber, 1997 4.4.2 pin mapping between mii interface and 10mbps serial interface m ii interface 10mbps serial interface sy mbol type symbol type name & functions mm _ rxd[3 : 1] ttl in (5vt) not used by serial interface ports. has a weak internal pull-up resistor. mm_rxd[0] ttl in (5vt) tm_rxd ttl in (5vt) receive data C (one for each serial interface port) a receive data stream. mm_rxdv ttl in (5vt) not used by serial interface ports. has a weak internal pull-up resistor. mm_rxc ttl in (5vt) tm_rxc ttl in (5vt) receive clock C (one for each serial interface port) mm_rxer ttl in (5vt) not used by serial interface ports. has a weak internal pull-up resistor. mm_txer cmos out put not used by serial interface ports. mm_txc ttl in (5vt) tm_txc ttl in (5vt) transmit clock C (one for each serial inter- fa ce port) a continuous clock input with 35% to 65% duty cycles. mm_txen cmos out put tm_txen cmos out put transmit enable C (one for each serial inter- face port) mm_txd[0] cmos out put tm_txd cmos out put transmit data C (one for each serial interface port) a transmit data stream. mm_txd[1] cmos out put not used by serial interface ports mm_txd[2] cmos out put tm_l pbk cmos out put loop back enable C (one for each serial in- terface port) the polarity of this signal is pro- grammable via port configuration register mm_txd[3] cmos out put tm_fd cmos out put full duplex mode C (one for each serial in- terface port) the polarity of this signal is pro- grammable via port configuration register mm_col ttl in (5vt) tm_col ttl in (5vt) collision detected C (one for each serial in- terface port) mm_crs ttl in (5vt) tm_crs ttl in (5vt) carrier sense C (one for each serial interface port) mm_lnk ttl in (5vt) tm _lnk ttl in (5vt) link status C (one for each port) the polarity of this signal is programmable via port configu- ra tion register note: m is the port number [3:0]. th ese signals have programmable output polarity. 4.5 test facility sy mbol type name & functions t_ mode cmos i/o ts test mode selection & test output C set test mode upon reset, and provides test status output during test mode
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 21 rev. 4.0 Cdecem ber, 1997 5. dc specification 5.1 absolute maximum ratings storage temperature -65 c to +150 c o perating temperature 0 c to +70 c supply voltage v dd with respect to v ss +3.0 v to +3.6 v voltage on 5v tolerant input pins -0.5 v to (v dd + 2.5 v) voltage on other pins -0.5 v to (v dd + 0.5 v) stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 5.2 dc characteristics v dd = +3.0 v to +3.6 v t ambient = 0 c to +70 c preliminary symbol parameter description min typ max unit f osc frequency of operation ( -33) 20 33.3333 mhz frequency of operation ( -40) 20 40.0000 mhz frequency of operation (-50) 20 50.0000 mhz i dd supply power C @ 33.3333 mhz (v dd =3.3 v) tbd ma supply power C @ 40 mhz (v dd =3.3 v) tbd ma supply power C @ 50 mhz (v dd =3.3 v) tbd ma v oh-cmos ou tput high voltage (cmos) i oh = maxi mum v dd - 0.5 v v ol-cmos ou tput low voltage (cmos) i ol = maxi mum 0.45 v v oh-ttl ou tput high voltage (ttl) i oh = maxi mum 2.4 v v ol-ttl ou tput low voltage (ttl) i ol = maxi mum 0.45 v v ih-cmos input high voltage (cmos) vdd x 70% v dd + 10% v v il-cmos input low voltage (cmos) -0.5 vdd x 30% v v ih-ttl input high voltage (ttl) 2.0 v dd + 10% v v il-ttl input low voltage (ttl) -0.3 +0.8 v v ih-5vt input high voltage (ttl 5v tolerant) 2.0 v dd + 1.8 v v il-5vt input low voltage (ttl 5v tolerant) -0.3 +0.8 v i li input leakage current (0.1 v ) v in ) v dd ) (a ll pins except those with internal pull- up/pull-down resistors) 10 a i lo ou tput leakage current (0.1 v ) v out ) v dd ) 15 a i ih input leakage current v ih = v dd - 0.1 v (p ins with internal pull-down resistors) 60 a i il input leakage current v il = 0.1 v (p ins with internal pull-up resistors) -60 a c in input capacitance 8 pf c out ou tput capacitance 8 pf c i/o i/o capacitance 10 pf notes:
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 22 rev. 4.0 Cdecem ber, 1997 6. ac specification 6.1 xpressflow bus interface: s17 s19 s21 s23 s27 s29 s31 s33 s18 s20 s22 s24 s28 s30 s32 s34 s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_gnt# s_ovld# xpressflow bus interface C input setup and hold timing s1-min s12 s2-min s13 s3-min s14 s4-min s15 s_clk s_d[31:0] s_msgen# s_eof# s_irdy xpressflow bus interface C output float delay timing s1-min s1-max s2-min s2-max s3-min s3-max s4-min s4-max s6-min s6-max s7-min s7-max s8-min s8-max s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_req# xpressflow bus interface C output valid delay timing
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 23 rev. 4.0 Cdecem ber, 1997 -33 -40 -50 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: s1 s_d[31:0] output valid delay 6 20 5 18 4 15 c l = 50pf s2 s_msgen# output valid delay 6 20 5 18 4 15 c l = 50pf s3 s_eof# output valid delay 6 20 5 18 4 15 c l = 50pf s4 s_irdy output valid delay 6 20 5 18 4 15 c l = 50pf s6 s_tabt# output valid delay 6 20 5 18 4 15 c l = 50pf s7 s_hpreq# output valid delay 6 20 5 18 4 15 c l = 50pf s8 s_req# output valid delay 6 20 5 18 4 15 c l = 20pf s12 s_d[31:0] output float delay 15 13 10 s13 s_msgen# output float delay 15 13 10 s14 s_eof# output float delay 15 13 10 s15 s_irdy output float delay 15 13 10 s17 s_d[31:0] input set-up time 5 4.5 4 s18 s_d[31:0] input hold time 2 1.5 1.5 s19 s_msgen# input set-up time 5 4.5 4 s20 s_msgen# input hold time 2 1.5 1.5 s21 s_eof# input set-up time 5 4.5 4 s22 s_eof# input hold time 2 1.5 1.5 s23 s_irdy input set-up time 5 4.5 4 s24 s_irdy input hold time 2 1.5 1.5 s27 s_tabt# input set-up time 5 4.5 4 s28 s_tabt# input hold time 2 1.5 1.5 s29 s_hpreq# input set-up time 5 4.5 4 s30 s_hpreq# input hold time 2 1.5 1.5 s31 s_gnt# input set-up time 5 4.5 4 s32 s_gnt# input hold time 2 1.5 1.5 s33 s_ovld# input set-up time 5 4.5 4 s34 s_ovld# input hold time 2 1.5 1.5 ac ch aracteristics C xpressflow bus interface
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 24 rev. 4.0 Cdecem ber, 1997 6.2 cpu bus interface: p16-min p15 p_clk p_d[31:0] cpu bus interface C output float delay timing p 16-min p16-max p 17-min p17-max p 18-min p18-max p_clk p_d[15:0] p_rdy# p_int cp ub us interface C output valid delay timing p1 p3 p5 p7 p9 p11 p2 p4 p6 p8 p10 p12 p_clk p_rst# p_ads# p_w/r# p_cs# p_a[11:1] p_d[15:0] cp ub us interface C input setup and hold timing -33 -40 -50 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: p1 p_rst# input setup time 5 4.5 4 p2 p_rst# input hold time 2 1.5 1.5 p3 p_ads# input set-up time 5 4.5 4 p4 p_ads# input hold time 2 1.5 1.5 p5 p_w/r# input set-up time 5 4.5 4 p6 p_w/r# input hold time 2 1.5 1.5 p7 p_cs# input set-up time 5 4.5 4 p8 p_cs# input hold time 2 1.5 1.5 p9 p_a[11:1] input set-up time 5 4.5 4 p10 p_a[11:1] input hold time 2 1.5 1.5 p11 p_d[31:0]# input set-up time 5 4.5 4 p12 p_d[31:0]# input hold time 2 1.5 1.5 p15 p_d[31:0]# output float delay 15 13 10 p16 p_d[31:0]# # output valid delay 620518415c l = 60pf p17 p_rdy# output valid delay 620518415c l = 60pf p18 p_int# output valid delay 620518415c l = 20pf ac characteristics -- cpu bus interface
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller ? 1997 zarlink semiconductor inc. page: 25 rev. 4.0 Cdecem ber, 1997 6.3 local memory interface: l1 l2 l_clk l_d[31:0] local memory interface C input setup and hold timing l3-min l10 l_clk l_d[31:0] local memory interface C output float delay timing l3-min l3-max l4-min l4-max l5-min l5-max l6-min l6-max l7-min l7-max l8-min l8-max l9-min l9-max l_clk l_d[31:0] l_a[19:2] l_cs[3:0]# l_adsc# l_bwe[3:0]# l_we#] l_oe# local memory interface C output valid delay timing -33 -40 -50 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: l1 l_d[31:0]# input set-up time 5 4.5 4 l2 l_d[31:0]# input hold time 2 1.5 1.5 l3 l_d[31:0]# output valid delay 6 20 5 18 4 15 c l = 30pf l4 l_a[19:2] output valid delay 6 20 5 18 4 15 c l = 30pf l5 l_cs[3:0]# output valid delay 6 20 5 18 4 15 l6 l_adsc# output valid delay 6 20 5 18 4 15 c l = 30pf l7 l_bwe[3:0]# output valid delay 6 20 5 18 4 15 c l = 30pf l8 l_we# output valid delay 6 20 5 18 4 15 c l = 10pf l9 l_oe# output valid delay 6 20 5 18 4 15 c l = 10pf l10 l_d[31:0]# output float delay 15 13 10 ac characteristics C local memory interface
preliminary data sheet xpressflow-2001 series C ea-224 ethernet switch chip-set 4-port 10/100m ethernet access controller this document contains advance information on a product under development. zarlink semiconductor inc. reserves the right to make an yc hanges without notice. 7. packaging information 352-pin bga (35x35x2.33mm) a b 35.00 +/- 0.20 pin 1 i.d. 2.33 +/-0.13 0.60 +/-0.10 c 31.75 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1.27 2 4 1 3 6 8 5 7 10 12 9 11 20 19 18 17 14 16 13 15 22 26 25 23 21 24 0.75 dia +/- 0.15 (352x) 1.17 ref 0.56 ref 32.00 ref 24.00 ref ? 1997 zarlink semiconductor inc. 400 march road o ttawa, ontario, canada k2k 3h4 rev. 4.0 december 1997 tel. 613 592 0200, fax: 613 592 1010 web site: www.zarlink.com
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes: dimension conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 35.20 34.80 30.00 ref 352 1.27 0.60 0.90 30.00 ref 1.17 ref 34.80 min 0.50 2.20 35.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 5. not to scale. 3. seating plane is defined by the spherical crowns of the solder balls. d e e d1 e1 a2 a1 a
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of MEA224

	To Download MEA224 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .